Vitaly Chipounov & Djordje Jevdjic winners of Intel PhD Fellowship

© 2013 EPFL

© 2013 EPFL

Vitaly Chipounov and Djordje Jevdjic, have been awarded the Intel Doctoral Student Honor Programme Award for the 2013-2014 academic year. Intel awards exceptional PhD candidates pursuing leading-edge innovation in fields related to company's business and research interests.

The Intel PhD Fellowship Program grants fellowships to outstanding PhD students in Engineering, Computer Science, Social Science, and other technical related majors. This is a prestigious and highly competitive program with a limited number of fellowships awarded annually. Selected students are recognized as being amongst the best in their areas of research.

Vitaly Chipounov from the Dependable Systems Lab (DSLab), received the award for S2E, a system for building program analysis tools, now being used by dozens of teams around the world.
S2E is a platform for analyzing the properties and behavior of software systems. Vitaly and his colleagues built upon it several tools for automated testing of kernel- and user-mode binaries, automated porting of binary device drivers, and comprehensive performance profiling. The S2E platform is open sourced and available here, with a ready-to-use demo, documentation, and tutorials. S2E won the best paper award at ASPLOS 2011. Three years after release, S2E acquired a rapidly growing user community of more than 150 members and is actively used by researchers and companies around the world in order to test distributed networks, analyze file systems, detect private data leaks in smartphone apps, perform security analysis, and more.

Djordje Jevdjic from the Parallel Systems Architecture Laboratory (PARSA), headed by Prof. Babak Falsafi, has been awarded the fellowship for his oustanding work on memory systems.
Djordje's research focuses on multi-gigabyte on-chip DRAM caches as a way to mitigate the memory bandwidth wall in future server processors. His design, called Footprint Cache, optimizes for all of cache hit rate, cache lookup latency and off-chip bandwidth at the same time, significantly outperforming existing designs in terms of both performance and energy efficiency.