PhD Defense of Arda Uran

This thesis aims to explore and exploit trade-offs in integrated circuits and systems to overcome the fundamental bottlenecks faced by future data acquisition and communication systems. Specifically, we target the emerging implantable neurotechnology and the advancing highspeed communication domains as case studies. The first part of the thesis addresses the extreme resource constraints of implantable neurotechnology. As the number of electrodes for neural recording reaches towards thousands, a single-chip solution is rendered infeasible in terms of both energy and area. To tackle this problem, we present an analog front-end architecture that applies various energy- and areasaving techniques to reduce the hardware resource demand of neural recording. The second challenge has been transferring the massive data throughput over a wireless link to allow neural recording in independent environments. Inspired by the previous ideas for compression and the emerging machine learning applications in neuroscience, we introduce an on-chip adaptive feature extraction framework to reduce the overall data rate to the feasible range. The second part of the thesis focuses on the timing uncertainty problem in high-speed communication systems. The increasing data rates in wireline and wireless transceivers, and the emerging need for multitransceiver architectures necessitate the lowest energy and area for the frequency synthesis, which contradicts the current jitter-cost trade-off paradigm. To allow the use of area-efficient ring oscillators for jitter-sensitive applications under low-power constraints, we introduce a multiphase feedback phase-locked loop architecture, which suppresses the oscillator phase noise over a larger bandwidth.