Patrick Denantes Memorial Prize 2023 announced

We’ve all heard of Moore’s Law – a prediction made by Gordon Moore, founder and former CEO of Intel – that the number of transistors on a microchip will double every two years, meaning that the speed and capability of our computers increase in parallel.

Now that Moore’s observation is coming to an end, and it is no longer possible to rely on general purpose hardware to meet today’s increasing needs for computation, big companies, such as Microsoft, Alibaba, Amazon and Google have begun to focus on custom hardware specialization and making their own chips.

Yet, it can cost up to half a billion dollars to create a new chip which means the majority of companies need to rely on Field-Programmable Gate Arrays (FPGAs), currently the only viable reconfigurable platform for creating custom hardware.

“FPGAs have been a reliable technology but what has happened recently is that they, themselves, have started facing scaling problems. As you scale transistors down to make more dense chips, you also have to scale down the wires that connect the individual transistors and as their cross section diminishes, they become slower and slower,” explains Stefan Nikolić, who worked in Professor Paolo Ienne’s Processor Architecture Laboratory.

This wiring challenge means that FPGAs suffer more from the adverse effects of scaling than other chips and, unlike in the past, they can no longer become faster by their previous design being slightly modified. To revolutionize chip design and overcome this problem, in his PhD thesis Automating the Design of Programmable Interconnect for Reconfigurable Architecture, Nikolić investigated whether it’s possible to automate the process of programmable interconnect design.

“This hasn’t been done before because it’s inherently difficult to find the right architecture, not just optimized for one concrete circuit, but essentially optimized to support many,” Nikolić says. “And we discovered that now really is the time to do this because FPGAs are currently the only way to democratize access to technology,” he continued.

Nikolić outlines several new algorithms in his thesis that demonstrate it is possible to automate this process, bringing many possible benefits to reconfigurable architecture design.

“Currently, FPGAs trail behind CPUs and GPUs in adopting new CMOS and Stefan's thesis may help FPGA manufacturers get out of the present impasse. Looking ahead, there might be a more speculative but very exciting impact: while FPGAs might not prove to be the ultimate computational devices of the future as some anticipate, they may well serve as a blueprint of future, hitherto unimagined, reconfigurable computing devices,” explained Nikolić’s supervisor, Professor Ienne. “Stefan's thesis offers a breakthrough: it empowers computer architects to craft the interconnect of innovative reconfigurable platforms without requiring extensive FPGA architecture expertise and potentially cutting down on months or years of experimentation,” Ienne continued.

There are some clear follow on goals to the PhD research, applying the new algorithms to different kinds of FPGAs to connect different parts of the architecture that haven't yet been tackled, and Nikolić believes there’s a lot left on the table in terms of performance optimization.

“I am very proud of the work, it was interesting and not something that we started looking into at the beginning and that we were hoping to see at the end. It is also a great honor and surprise to win the Patrick Denantes Memorial Award, it certainly wasn’t something I was expecting at the start of my PhD,” said Nikolić.

Patrick Denantes was an IC doctoral student who passed away in a mountain accident in 2009. The annual prize in Patrick’s name honors his memory. The prize is awarded by a jury and presented to the laureate at the School’s end-of-year event. Financial sponsorship is provided by the Denantes family and the Nokia Research Center. The laureate receives a sum of CHF5,000.