Neurotechnology research at LIONS
Invasive brain recording is a promising technology for helping people who suffer from severe neurological disorders. Recorded brain signals can be used to control brain-machine interfaces with high precision, or to identify disease biomarkers with high sensitivity. Future wireless brain implants aim to process thousands of electrodes. However, processing and sending data from this many electrodes using a single chip has been an outstanding challenge due to the resource scarcity of implanted devices.
Arda Uran, a PhD student at LIONS, has developed a wireless multichannel neural recording system-on-chip with an unprecedented resource efficiency in collaboration with researchers from EPFL. The chip in 65nm CMOS technology is composed of modular recording channels, each with an individual sensor front-end and a feature extractor to feed machine learning applications. The sensor front-end of the chip digitizes neural potentials with 12 times more energy-area efficiency compared to the state of the art. The on-chip feature extractor reduces the wireless data rate by 80% and enables 5 times more channels to be transmitted on the same energy and bandwidth budget, without compromising classification performance.
The recording quality of the system was validated through an in vivo experiment on rats, and the classification performance was validated on human epilepsy databases. The results of this study point towards fully implanted and massively parallel wireless recording implants, which will unlock new possibilities in neurotechnology.
A. Uran, Y. Leblebici, A. Emami and V. Cevher, "An AC-Coupled Wideband Neural Recording Front-End with Sub-1 mm2×fJ/conv-step Efficiency and 0.97 NEF," in IEEE Solid-State Circuits Letters, vol. 3, pp. 258-261, 2020, doi: 10.1109/LSSC.2020.3013993.
A. Uran, K. Ture, C. Aprile, A. Trouillet, F. Fallegger, A. Emami, S. Lacour, C. Dehollain, Y. Leblebici, and V. Cevher, "A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS", 2021 IEEE Custom Integrated Circuits Conference (CICC), 2021, pp. 1-2, doi: 10.1109/CICC51472.2021.9431458.