Asea Brown Boveri Ltd. (ABB) Award 2012 - Giovanni Antonio Salvatore

"For having shown experimentally by incorporating a ferroelectric layer in the transistor and theoretically validated that a sub threshold slope of a MOS transistor can be less than 60 mV/decade and shown that these devices could be used as non-volatile memories or switches."

Abstract: The limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid approaches where other technologies add to the CMOS performance. Ferroelectrics in ultra-thin films has been investigated as a credible candidate for nonvolatile memory, and, more recently, proposed as a negative dielectric-constant material.
This thesis studies the performance of a ferroelectric transistor for low power memory and switch applications. An organic ferroelectric polymer, vinylidene uoride triuorethylene, P(VDF-TrFE), of 100nm and 40nm thickness has been successfully integrated into the gate stack of bulk and SOI MOSFET. The 1T ferroelectric FET memory cells show a programming time of ms at 9V as programming voltage and retention of few seconds. A subthreshold swing lower than 60mv/dec has been achieved in a ferroelectric transistor thanks to the voltage amplification arising from the ferroelectric material. This unique finding has been first measured in a 40nm P(VDF-TrFE)/10nm SiO2 gate stack MOSFET and then, confirmed, in a 100nm P(VDF-TrFE)/10nm SiO2 gate MOSFET with an intermediate contact between the two dielectrics.
A model based on Landau’s theory has been studied and experimentally validated to explain the temperature behavior of the device. It has been also demonstrated that, because of the divergence of the ferroelectric permittivity at the Curie temperature, Tc, a ferroelectric transistor has a maximum and a minimum, respectively of its transconductance and subthreshold swing, at Tc