Interview with EDAA awarded PhD graduate student
© 2011 EPFL
Ajay K. Verma, PhD graduate student from Professor Paolo Ienne, was awarded by the l'European Design and Automation Association (EDAA).
Dr Ajay K. Verma will receive the "EDAA Outstanding Dissertations Award 2010" for the excellence of his thesis "Pre-synthesis optimization of arithmetic circuits", in the field of new directions in logic and system designs. Dr Verma will receive the award at the DATE 2011 conference (March 14-18 in Grenoble, France).
INTERVIEW WITH AJAY K. VERMA:
What was the outstanding contribution of your thesis to the research in design, automation and test, and for which EDAA selected it?
Despite the impressive progress of logic synthesis in the past decade, the efficient synthesis of arithmetic circuits still remains a largely unsolved problem. Synthesis tools are extremely good in performing local optimizations, but very rarely change the architectural structure of the implementation. This is the reason why designers still rely on the circuit implementations designed manually by experts in the field.
This thesis analyzes the core problem in the synthesis of arithmetic circuits and presents a pre-synthesis optimization phase, which generates a near-optimal architectural implementation of the input circuit. The circuit implementations designed by the proposed method not only match the performance of the ones designed manually by experts, but in some case also exhibit better performance than the ones manually designed. Such is the case even for very well studied
circuits (e.g., multiplier, multi-input comparator).
How would you explain the subject of your thesis, “Pre-synthesis optimization of arithmetic circuits”, to the "man on the street"?
The speed of a microprocessor is governed by the maximum delay of the CPU instructions. Usually, arithmetic instructions (e.g., addition, multiplication, division) are the ones with longest delay.
Hence, arithmetic circuits have attracted significant attention of researchers, and their efficient implementation has been manually designed.
This thesis presents a method to automate this process. It starts with the description of an arithmetic instruction (in form of circuit), and generates an implementation which is nearly as fast as the one designed by an expert. In some cases, the generated implementation is even better than manually designed ones, e.g., our method generates a multiplier which is almost 15% faster than the state of art multipliers.
What did you do after your PhD in the School of Computer and Communications Science?
After finishing my Ph.D. I joined Nokia Gate5 GmbH, and since then I have been working there as a senior software engineer. Currently, I am working on improving the performance of routing queries in a road network by efficiently preprocessing the data.
BIOGRAPHY:
Ajay K. Verma did his bachelors from Indian Institute of Technology, Kanpur in May 2003. His bachelor thesis was to find an NC algorithm for the bipartite matching, and received the best thesis award. He joined EPFL in 2004, and worked as a doctoral student under the supervision of Prof. Paolo Ienne. His area of interest involves logic synthesis of arithmetic circuits and custom instruction set extension. During the doctoral study he was nominated for the best paper award in DAC-2007 and ASPDAC-2007, and received the best paper award in CASES-2007. After finishing the thesis, he joined Nokia Gate5 GmbH.