EPFL doctorate Award 2015 – Lukas Kull
© 2015 EPFL
High-Speed CMOS ADC Design for 100 Gb/s Communication Systems, EPFL thesis n° 6037 (2014)
Thesis directors: Prof. Y. Leblebici, Dr T. Toifl
“For developing the analytical modeling framework for performance optimization in high-speed successive approximation (SAR) based analog-to-digital converters (ADC), and for his groundbreaking work in designing an entire range of record‐breaking time‐interleaved ADCs achieving the highest demonstrated sampling frequencies in their category.”
Analog-to-Digital Converters (ADCs) constitute the very interface between the “real” and the digital world. Besides converting images and sound to the digital domain, ADCs operating at extremely high conversion rates enable ultra-high-speed data transmission over wireless, electrical and optical channels.
In next-generation optical communications links that connect cities, countries and continents, for example, the absence of fast ADCs was a key limitation for achieving higher data rates. Thus faster, but energy-efficient ADCs were required to enable complex digital equalization of long-distance fiber-channels.
This dissertation, performed as part of a collaboration between EPFL and IBM Research – Zurich, presents the world’s fastest CMOS ADC to date. This ADC features a new architecture for an 8-bit 64× interleaved CMOS ADC running at up to 100 GHz sampling frequency. It fulfills all specifications for 100 Gb/s long-distance communication over optical fiber-channels. Furthermore, an ADC with 36 GHz sampling rate for 100 Gb/s Ethernet for electrical links (backplane or copper wire), and two power-optimized ADCs running at 8.8 and 1.2 GHz were demonstrated. All circuits exhibit record energy-efficiency and record low silicon-area use by implementing various new circuit techniques: The 100 GS/s ADC occupies less than 0.5 mm2 and is 50% faster than what has been shown to date, at only < 1 W power consumption.
